1. Technical Field
The embodiments disclosed herein relate to a semiconductor integrated circuit and, more particularly, to a duty cycle correction circuit of a semiconductor integrated circuit.
2. Related Art
In general, a semiconductor integrated circuit includes a clock signal controlled such that the duty cycle of the clock signal is held to 50%. In the case where the duty cycle of the clock signal is not 50%, a duty cycle correction circuit is required to correct the distorted clock signal.
FIG. 1 is a schematic block diagram of a conventional duty cycle correction circuit. In FIG. 1, the duty cycle correction circuit 1 includes a first differential amplifier 10 and a second differential amplifier 20. The first differential amplifier 10 includes a first resistor R1, a second resistor R2, a first NMOS transistor N1, a second NMOS transistor N2, and a first current source CS1. In addition, the second differential amplifier 20 includes a third NMOS transistor N3, a fourth NMOS transistor N4, and a second current source CS2.
The first differential amplifier 10 buffers and amplifies an external supply voltage VDD with respect to a clock signal ‘clk’ and a complementary clock signal ‘clkb’, which is out of phase with the clock signal ‘clk’, and then outputs an output signal ‘out’ and a complementary output signal ‘outb’, which is out of phase with the output signal ‘out’. The second differential amplifier 20 receives duty control signals ‘dcc’ and ‘dccb’ based on a voltage difference between the output signal ‘out’ and the complementary output signal ‘outb’, and then controls voltage levels of first and second nodes (Node1) and (Node2) at which the output signal ‘out’ and the complementary output signal ‘outb’ are output, respectively. The duty cycles of the clock signal ‘clk’ and the complementary clock signal ‘clkb’ are controlled by changing the voltage levels of the output signal ‘out’ and the complementary output signal ‘outb’.
In FIG. 1, the duty cycle correction circuit 1 employs a pair of differential amplifiers 10 and 20 to correct the duty cycle, wherein the first differential amplifier 10 is used only as a buffer. When the second differential amplifier 20 is connected in parallel with the first differential amplifier 10, the two differential amplifiers function as the duty cycle correction circuit. Accordingly, since current sources, i.e., a first current source and a second current source, are needed for the differential amplifiers 10 and 20, respectively, current consumption is increased.